It will be appreciated that integrated circuits (IC's) and/or semiconductor chips can be represented in both schematic and layout form. In schematic form, electrical elements or components of the circuit are represented as known symbols, and the symbols are interconnected to one another according the circuit design. It will also be appreciated, however, that the symbols bear little to no resemblance to the actual elements because the elements are implemented in and on a semiconductor substrate, such as a silicon wafer or one or more die on the wafer as regions of silicon are treated in one or more manners and/or as one or more layers formed upon the silicon are treated in one or more manners, such as by being doped with dopant atoms and/or etched to comprise a certain pattern, for example. As such, the circuit can also be depicted in layout form where the elements and particular arrangement thereof correspond more closely to their actual implementation in silicon.
It will be appreciated that integrated circuits are generally designed by drawing a schematic of the circuit such that electrical elements are interconnected to achieve a desired result. The circuit schematic is then converted to a layout form so that the circuit can be fabricated in silicon. A layout versus schematic (LVS) comparison can then be performed (e.g., in computer software) to verify that everything in the schematic is in fact in the physical implementation, or rather that the physical implementation of the circuit matches its logical (schematic) definition.
Nevertheless, some issues may persist in transferring the design from a circuit schematic to layout form, and such issues may not be detectable by LVS comparisons and/or other conventional verification techniques. By way of example, it can be appreciated that certain elements or groupings of elements are commonly isolated from other elements in integrated circuits. The elements are generally isolated from one another by isolated pwells within which the elements are formed. The tanks or isolated pwells are defined above one or more buried layers within the semiconductor substrate and are surrounded by a substantially circular wall of dopant atoms implanted into the substrate, called an nwell. However, multiple isolated pwell tanks may, in certain instances, be coupled to the same potential or bias voltage (which may also be referred to as being coupled to the same node). Additionally, this potential may, at times, correspond to the potential of the substrate where one or more tanks are shorted or otherwise coupled to the substrate.
Having isolation pwells at the same potential and/or at the potential of the substrate can, however, lead to problems that are undetectable by LVS comparisons and/or other conventional verification techniques. For example, where two tanks are coupled to the same node, conventional verification programs would not be able to detect a situation where one or more elements are formed within the wrong tank and/or where multiple elements are not grouped together in a desired manner, for example. An LVS program would not detect these problems, for example, because the number of elements in the schematic would match the number of elements in the layout diagram and all of the elements would be subject to the appropriate node voltage (e.g., in accordance with the circuit design). Similarly, where a tank is shorted to a substrate, an LVS program would not detect a situation where devices are inadvertently formed outside (or inside) of the tank, but are supposed to be in (or out of) the tank since the number of elements in the schematic would match up with the number of elements in the layout diagram and the elements would be subject to the appropriate bias (e.g., substrate) voltage.
Accordingly, a scheme that facilitates isolated pwell tank verification would be desirable.